1. Field of the Invention
The present invention relates to a test system of integrated circuits, and more particularly, to a test system of integrated circuits for reducing test signal loss.
2. Description of the Prior Art
Semiconductor devices and integrated circuits require a lot of tests during various manufacture procedures. Since current integrated circuits can process high-speed signals, the high-speed test is required so as to increase the difficulty performance in testing. When the integrated circuits are tested, signal loss and delay would exist between the transmission lines and interfaces of the integrated circuits. Thus, the test system has to separate the signal of the driver from the signal of the receiver. This test system is called “Fly-by”.
Please refer to FIG. 1. FIG. 1 is a schematic view of a test system according to the prior art. The test system comprises a tester 10, a first signal line 12, a second signal line 14, a probe card 16 as a testing medium and a device under test (DUT) 19. The tester 10 has a driver 21 and a receiver 29. The driver 21 is coupled to a first contact C1 of the probe card 16 via the first signal line 12. The receiver 29 is coupled to a second contact C2 of the probe card 16 via the second signal line 14. The first contact C1 and the second contact C2 are coupled to the same solder pad B. The solder pad B is electrically connected to a bonding pad A of the DUT 19 via a corresponding needle. The driver can output a test signal. The test signal is transmitted to the solder pad B via the first contact C1, then transmitted to the bonding pad A via the corresponding needle, finally transmitted to the DUT 19 via the bonding pad A. After the DUT 19 responses the test signal, the test signal is transmitted to the receiver 29 via the bonding pad A, solder pad B, and the second contact C2. When the test signal is transmitted from the DUT 19 to the receiver 29, a great signal loss is generated between the solder pad B and the bonding pad A, because the test signal at the solder pad B is influenced by the impedance of the first signal line 12.
Please refer to FIG. 2. FIG. 2 is a schematic circuitry of the test system in FIG. 1. The equivalent circuitry inside the tester 10 (as shown in FIG. 1) comprises the driver 21, a first impedance 22, a first resistor 23, the receiver 29, a second impedance 28 and a second resistor 27. The output voltage of the tester 10 is Vout. One end of the first resistor 23 and one end of the second resistor 27 are coupled to a terminal voltage Vtt. a third impedance 24 and a fourth impedance 26 are the equivalent impedances of the first signal line 12 and the second signal line 14 respectively. The fifth impedance 25 is the equivalent impedance of the needle of the probe card 16. Assume the value of the first impedance 22, the second impedance 28, the third impedance 24, the fourth impedance 26, and the fifth impedance 25 are 50Ω respectively, and the value of the first resistance 23 and the second resistance 27 are 50Ω respectively. When the DUT 19 responses the test signal, for the solder pad B, the equivalent impedance of the first signal line 12 and the equivalent impedance of the second signal line 14 can be regarded as the parallel connection. Thus, the voltage of the solder pad B is equal to the equation:
  Vb  =                    (                  Vout          -          Vtt                )            ×                        (                      25            +            25                    )                          (                      25            +            25            +            50                    )                      =                  (                  Vout          -          Vtt                )            ×      0.5      
This shows the signal loss at solder B is 50% more than the output voltage.
In conclusion, when the test system performs the high-speed test, the signal of the driver should be separated from the signal of the receiver. Thus, the driver transmits the test signal to the DUT via the first signal line, and then the test signal is transmitted to the receiver from the DUT via the second signal line. However, the test signal from the DUT is influenced by the impedance of the first signal line seriously so as to result in the signal loss. The large signal loss may fail to read the information of the signal correctly.